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| Preliminary Specification N-Channel Dual-Gate MOSFET Description The TMF3202Z is an enhancement type N-channel field-effect transistor. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good crossmodulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT343 micro-miniature plastic package. TMF3202Z SOT343 Unit in mm 2 3 1 4 Features - Gain controlled amplifier with AGC - Integrated gate protection diodes - High AGC-range, high gain, low noise figure Applications - Gain controlled input stage for UHF and VHF tuners - Professional communications equipment 1. SOURCE 2. DRAIN 3. GATE 2 4. GATE 1 Absolute Maximum Ratings (Ta = 25 ) Parameter Drain-Source Voltage Drain Current Gate 1 Current Total Power Dissipation Storage Temperature Operating Junction Temperature Symbol VDS ID IG1 Ptot Tstg Tj Ratings 10 30 10 200 -65 ~ 150 150 Unit V mA mA mW Caution : Electro Static Discharge sensitive device, observe handling precaution http://www.tachyonics.co.kr October. 2005. Page 1 of 8 Rev. 1.0 Preliminary Specification DC Characteristics ( Tj = 25 , unless otherwise specified ) PARAMETER Drain-source breakdown voltage Gate1-source breakdown voltage Gate2-source breakdown voltage Forward source-gate1 voltage Forward source-gate2 voltage Gate1-source threshold voltage Gate2-source threshold voltage Drain-source current Gate1 cut-off current Gate2 cut-off current SYMBOL V(BR)DSS V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S CONDITION VG1-S=VG2-S=0; ID=10 VG2-S=VDS=0; IG1-S=10 VG1-S=VDS=0; IG2-S=10 VG2-S=VDS=0; IS-G1=10 VG1-S=VDS=0; IS-G2=10 VDS=5V; VG2-S=4V; ID=100 VDS=5V; VG1-S=4V; ID=100 VG2-S=4V; VDS=5V; RG=62 VG1-S=5V; VG2-S=VDS=0 VG2-S=5V; VG1-S=VDS=0 MIN. 10 6 6 0.5 0.5 0.3 0.3 8 - TMF3202Z MAX. 10 10 1.5 1.5 1.0 1.2 16 10 10 UNIT V V V V V V V AC Characteristics ( Common source; Ta = 25 , VG2-S = 4V, VDS =5V, ID =12mA ;unless otherwise specified ) PARAMETER Forward transfer admittance Input capacitance at gate1 Input capacitance at gate2 Output capacitance Reverse transfer capacitance SYMBOL IyFSI Cig1-ss Cig2-ss Coss Crss CONDITIONS MIN. TYP. MAX. UNIT Tj=25 f=1MHz f=1MHz f=1MHz f=1MHz f=200MHz; Zi = S11 , Zo = S22 * * 25 30 27 24 90 30 1.7 3.3 0.9 15 33 30 27 1.2 1.5 - 40 2.2 25 2.0 - mS fF Power gain Gtr f=400MHz; Zi = S11*, Zo = S22* f=800MHz; Zi = S11*, Zo = S22* f=400MHz; Zi = S11 opt(NF) Noise figure NF f=800MHz; Zi = S11 opt(NF) k=1%, fw=50MHz; funw=60MHz AGC = 0dB Cross-modulation X mod k=1%, fw=50MHz; funw=60MHz AGC = 10dB k=1%, fw=50MHz; funw=60MHz AGC = 40dB - 92 - 100 105 - http://www.tachyonics.co.kr October. 2005. Page 2 of 8 Rev. 1.0 Preliminary Specification Equivalent circuit (Top view) 3 4 Making 3 TMF3202Z 4 2 tachyonics X1 1 3 4 2 2 3 4 2 tachyonics X2 1 DB1 2 1 1 1 Diode DIODE2 1 Diode DIODE1 2 Pin Configuration PIN 1 2 3 DESCRIPTION SOURCE DRAIN GATE2 GATE1 Test circuit V_DC VAGC 1 1 R RAGC R=10 kOhm 2 2 2 1 4 C CAGC C=4.7 nF 1 C CD C=4.7 nF 1 2 2 R RL R=50 Ohm 1 1 2 1 1 C CDB C=4.7 nF 1 C CIN C=4.7 nF 1 R RSOURCE R=50 Ohm 2 1 V_AC SRC1 1 2 1 2 1 R RIN R=50 Ohm R RGB R=68 kOhm tachyonics X2 1 V_DC VGB 1 2 1 Diode DIODE1 1 1 1 2 1 2 3 4 2 2 3 4 2 tachyonics X1 1 2 L LD L=2.2 uH 2 1 Diode DIODE2 2 1 V_DC VDB Fig1. Test Cross-modulation test set-up http://www.tachyonics.co.kr October. 2005. Page 3 of 8 Rev. 1.0 Scattering parameters Preliminary Specification Graphs TMF3202Z ID [ m A ] 45 40 35 30 25 20 15 10 5 0 0.00 0.50 1.00 1.50 2.00 2V VG2=4V 3.5V 3V 2.5V ID [ m A ] 30 25 20 15 10 V G1-S : 1.5V 1.4V 1.3V 1.2V 1.1V 1V 0.9V 1.5V 5 1V 0 2.50 VG1-S [V] 0 1 2 3 4 5 6 V DS [V ] 7 VDS =5V, Tj = 25 Fig.2 Transfer characteristics 300 IG 1 [ u A ] VG2=4V 3.5V 3V VG2-S = 4V, Tj = 25 Fig3. Output characteristics | y fs| [m S ] 250 40 35 30 25 4V 3.5V 3V 200 2.5V 150 2V 20 15 2.5V 100 1.5V 10 5 0 50 1V VG2-S = 2V 0 4 8 12 16 20 ID [mA] 0 0.00 0.50 1.00 1.50 2.00 VG1-S [V] 2.50 VDS =5V, Tj = 25 Fig.4 Gate1 Current as a function of gate1 Voltage VDS =5V, Tj = 25 Fig5. Forward transfer admittance as a function of drain current http://www.tachyonics.co.kr October. 2005. Page 4 of 8 Rev. 1.0 Preliminary Specification TMF3202Z Graphs ID [ m A ] ID [ m A ] 20 16 14 12 10 8 16 12 8 6 4 2 4 0 0 20 40 60 80 100 IG1 [uA] 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGG [V] VDS= 5V, V G2-S = 4V, Tj = 25 Fig6. Drain current as a function of gate1 current VDS= 5V, V G2-S = 4V, RGB=62, Tj = 25 Fig7. Drain current as a function of gate1 supply voltage 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 RG1 = 33K 39K 51K ID [ m A ] ID [ m A ] 20 14 12 10 VGG = 5V 4.5V 4V 3.5V 3V 62K 75K 92K 100K 8 6 4 2 0 5 6 VGG=VDS [V] 0 1 2 3 4 5 6 VG2-S [V] V G2-S = 4V, Tj = 25 , RGB= (Connected to VGG) Fig8. Drain current as a function of gate1 and drain supply voltage ; see Fig1 VDS= 5V, Tj = 25 , RGB=62 Fig9. Drain current as a function of gate2 voltage http://www.tachyonics.co.kr October. 2005. Page 5 of 8 Rev. 1.0 Preliminary Specification Graphs TMF3202Z IG 1 [ u A ] 70 60 50 40 30 20 10 0 0.00 3.5V 3V VGG : 5V 4.5V 4V 0 G a in r e d u c t io n [ d B ] -10 -20 -30 -40 -50 1.00 2.00 3.00 4.00 5.00 6.00 VG2-S [V] 0 1 2 3 4 VAGC [V] VDS= 5V, RGB= 62, Tj = 25 ;Connected to VGB Fig10. Gate1 current as a function of gate2 voltage f=50MHz, Pin=-30dBm, VDS= 5V, VGB= 5V, RGB=62 Tj = 25 Fig11. Typical Gain reduction as a function of AGC Voltage ; see Fig1 ID [ m A ] 14 12 10 8 6 4 2 0 0 10 20 30 40 50 gain reduction [dB] f=50MHz, Pin=-30dBm, VDS= 5V, VGB= 5V, RGB=62 Fig12. Drain current as a function of gain reduction ; see Fig1 http://www.tachyonics.co.kr October. 2005. Page 6 of 8 Rev. 1.0 Preliminary Specification TMF3202Z Graphs Y iS [ m S] | yrs | [ u S ] 100 10 rs 100 100 -100 bis 1 10 -10 10 |yrs| gis 0 10 100 1000 f [MHz] 1 10 100 -1 1 1000 f [MHz] VDS= 5V, V G2-S = 4V Fig13. Input admittance as a function of frequency VDS= 5V, V G2-S = 4V Fig14. Reverse transfer admittance and phase as a function of frequency | yfs | [ m S ] |yfs| fs [ d eg ] 100 -100 100 10.00 bos 1.00 Y o S [ m S] 10 -10 10 fs 0.10 gos 1 10 100 -1 1 1000 0.01 10 100 1000 f [MHz] f [MHz] VDS= 5V, V G2-S = 4V Fig15. Forward transfer admittance and phase as a function of frequency VDS= 5V, V G2-S = 4V Fig16. Output admittance as a function of frequency http://www.tachyonics.co.kr Octorber. 2005. Page 7 of 8 Rev. 1.0 rs [ d e g ] 1000 -1000 1000 Preliminary Specification Scattering parameters (VG2-S = 4V, VDS =5V, ID =12mA, Ta = 25 ) Input Reflection Coefficient TMF3202Z Reverse Transmission, dB 0 -20 dB(S(1,2)) freq (10.00MHz to 1.000GHz) S(1,1) -40 -60 -80 1E7 1E8 freq, Hz Output Reflection Coefficient 1E9 Forward Transmission, dB 12 10 8 dB(S(2,1)) 6 4 2 0 1E7 S(2,2) 1E8 freq, Hz 1E9 freq (10.00MHz to 1.000GHz) VDS=5V, VG2-S=4V, ID=12mA f (MHz) 50 100 200 300 400 500 600 700 800 S11 Magnitude (ratio) 0.897 0.915 0.952 0.938 0.912 0.836 0.863 0.830 0.800 S21 Angle (deg) 0.974 -5.323 -17.920 -27.300 -35.160 -43.000 -50.800 -57.600 -63.470 S12 Angle (deg) 171.7 165.5 153.1 141.5 130.8 120.1 110.1 98.8 87.8 S22 Angle (deg) 93.0 91.7 89 89.2 92.6 95.6 100.4 104.6 110.7 Magnitude (ratio) 3.93 3.81 3.58 3.40 3.20 3.04 2.89 2.75 2.62 Magnitude (ratio) 0.001 0.001 0.002 0.002 0.003 0.004 0.004 0.004 0.004 Magnitude (ratio) 1.006 0.998 0.982 0.968 0.966 0.964 0.968 0.968 0.973 Angle (deg) -1.86 -4.89 -10.97 -16.13 -20.8 -26.01 -30.59 -35.8 -40.87 http://www.tachyonics.co.kr Octorber. 2005. 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